The present invention relates to a semiconductor memory device, and more particularly to an electrically erasable and programmable read-only memory (EEPROM).
An EEPROM is a semiconductor memory device for storing data. Semiconductor memory devices are classified into volatile memories and non-volatile memories according to whether stored data is retained even when a power is interrupted. Examples of the volatile memories include dynamic random access memory (DRAM) and static RAM (SRAM), and examples of the non-volatile memories include flash memory, erasable and programmable read-only memory (EPROM), EEPROM, and mask ROM. The EPROM erases stored data using ultraviolet light, which causes inconvenience in storing and erasing data. The EEPROM electrically erases stored data, which makes it easier to store, retain and erase data as compared to the EPROM. For this reason, the EEPROM is being widely used.
FIG. 1 is a schematic circuit diagram illustrating a cell block of a conventional semiconductor memory device. Particularly, a cell block of an EEPROM is described.
Referring to FIG. 1, the conventional EEPROM includes a memory cell 10, a sensing unit 20, and sensing enable control units 30 and 40. The memory cell 10 includes a unit cell transistor MREC for storing data, and a reference cell transistor MREF for storing reference data. A first sensing enable control unit 30 includes a first enable transistor T1 and a first biasing transistor T2. The first enable transistor T1 is turned on in response to an enable signal ENABLE. The first biasing transistor T2 supplies a predetermined bias voltage to an input terminal of the sensing unit 20. A second sensing enable control unit 40 includes a second enable transistor T3 and a second biasing transistor T4. The second enable transistor T3 is turned on in response to the enable signal ENABLE. The second biasing transistor T4 supplies a predetermined bias voltage to another input terminal of the sensing unit 20.
The unit cell transistor MREC has different threshold voltages, respectively, when stored data is 0 and 1. The reference cell transistor MREF has a threshold voltage in the range between the threshold voltage of the unit cell transistor MREC when data is 0, and the threshold voltage of the unit cell transistor MREC when data is 1. When the reference cell transistor MREF is turned on in response to the input of a read signal READ, the unit cell transistor MREC maintains a turned-on state or a turned-off state according to whether the data stored in the unit cell transistor MREC is 0 or 1.
In the sensing unit 20, two transistors T7 and T8 compare a signal from the reference transistor MREF with a signal from the unit cell transistor MREC, and a comparison result signal VOUT is output. If a threshold voltage of the unit cell transistor MREC is higher than that of the reference cell transistor MREF, the unit cell transistor MREC is not turned on and thus the sensing unit 20 outputs the comparison result signal VOUT having a logic high level. If the threshold voltage of the unit cell transistor MREC is lower than that of the reference cell transistor MPREF, the unit cell transistor MREC is turned on and thus the sensing unit 20 outputs the comparison result signal VOUT having a logic low level.
As described above, the conventional EEPROM requires the reference cell transistor MPREF for a data read operation, and a data access time increases by the time necessary for the sensing unit 20 to perform the comparison operation.
Also, as the level of the power voltage used in the memory device is lowered, a difference between the threshold voltage of the unit cell transistor MREC and the threshold voltage of the reference cell transistor MPREF decreases. Accordingly, a time required for the sensing operation of the sensing unit 20 increases. Furthermore, because the sensing unit 20 includes a differential amplifier, current consumption increases in the sensing operation.